1. Field of the Invention
The present invention relates, in general, to the design of digital circuits, and more particularly to the reduction of delay times associated with relatively long lines in complex digital integrated circuits (ICs).
2. Description of Related Art
Modern very-large-scale integration (VLSI) techniques enable design engineers to combine many independent components, or functional blocks, on a single piece of silicon. Examples of typical functional blocks are floating point units, input buffers, and dynamic memories. Such blocks are combined to form e.g. a complete microprocessor as a single IC.
Complex ICs, such as those of the Sparc family of microprocessors available from Sun Microsystems of Mountain View, Calif., are typically designed by teams of design engineers, working in parallel, each team creating the architecture for one or more functional blocks. Once the block-level architectures are completed, another team of design engineers creates an interconnect architecture for interconnecting the various functional blocks. When the IC is manufactured, the interconnect architecture is realized using a high-level interconnect process, such as a conventional metalization process.
The speed performance of a complex IC is largely determined by the propagation delay time of electrical signals travelling through the relatively long conductors, or long lines, used to define various signal paths of the interconnect architecture. Consequently, individual functional blocks are arranged so that interconnect lines forming signal paths between the functional blocks are as short as possible. Nevertheless, the operation of routing interconnect lines for complex ICs typically results in a number of signal paths formed by relatively long lines. Some of these signal paths limit the overall speed performance of the resulting IC, and are therefore identified as critical paths.
To improve the speed performance of a given IC, design engineers must pay particular attention to reducing the signal propagation delay time of critical paths. It is commonly known that inserting one or more repeater amplifiers (i.e. "repeaters") into a long line can decrease the signal propagation delay time through that line. Thus, where a critical path is formed by a relatively long line, the signal propagation delay associated with that critical path can be advantageously decreased by rerouting the long line to include a repeater amplifier.
Unfortunately, because critical paths are typically identified while designing the interconnect architecture for the IC, design engineers cannot be sure which lines form critical paths until after the block-level architectures are completed; thus, inserting repeater amplifiers into a long line to decrease the delay time associated with a critical path can require architectural changes to one or more functional blocks of the IC. (For a detailed discussion of the use of repeater amplifiers for optimizing delay times through long lines, see the aforementioned application entitled "Method of Optimizing Repeater Placement In Long Lines Of A Complex Integrated Circuit.")
Changing a block-level architecture to include one or more repeater amplifiers requires several steps. First, the IC design process must return from interconnect-level design to block-level design so that the design engineers responsible for the architecture of the discrete functional blocks of the IC (i.e., block-level design engineers) can make the required changes. Second, the addition of a repeater amplifier within a functional block is not trivial; the new repeater amplifier and/or the associated connections affects the placement and operation of adjacent components, which in turn effect the placement and operation of other components. In short, block-level modification takes time, an especially valuable commodity in the rapidly evolving semiconductor industry. Consequently, there is a need for a more timely method of decreasing the signal propagation delay time of critical paths on an IC.